Integrated circuits (ICs) consist of structured electrically semiconducting, non-conducting and conducting thin layers. These patterned layers are customarily prepared by applying a layer material, for example, by vapor deposition and patterning it by a microlithographic process. By way of the combination of the various electrically semiconducting, non-conducting and conducting layered materials the electronic circuit elements such as transistors, capacitors, resistors and wirings are fabricated.
The quality of an IC and of its function depends particularly on the precision with which the various layer materials can be applied and patterned.
However, with an increasing number of layers the planarity of the layers decreases significantly. This leads to the failure of one or more functional elements of the IC and, therefore, to the failure of the complete IC after a certain number of layers has been reached.
The decrease of the planarity of the layers is caused by the buildup of new layers on top of layers already patterned. By the patterning altitude differences are created which can add up to 0.6 μm per layer. These altitude differences add up from layer to layer and bring about that the next following layer can no longer be applied onto a planar surface but only onto an uneven surface. The first result is that the layer subsequently applied has an irregular thickness. In extreme cases, imperfections, defects in the electronic functional elements and lacking electrical contacts are caused. Moreover, uneven surfaces lead to problems with the patterning. In order to be able to create sufficiently small patterns, an extremely acute depth of focus is a necessary in the microlithographic process step. However, these patterns can only be imaged with acuity on a planar surface. The more the locations deviate from the planarity, the murkier the image becomes.
In order to solve this problem, a so-called chemical mechanical polishing (CMP) is carried out. The CMP causes a global planarization of the patterned surface by the removal of protruding features of the layer until a planar layer is obtained. Because of this, the subsequent buildup can take place on top of a planar surface exhibiting no altitude differences, and the precision of the patterning and of the functionality of the elements of the IC is maintained.
Typical examples for the global planarization are dielectric CMP, nickel phosphide CMP and silicium or polysilicium CMP.
In addition to the global planarization to overcome lithographical difficulties, there are two other important applications for CMP. One is to fabricate microstructures. Typical examples for this application are copper CMP, tungsten CMP or shallow trench isolation (STI) CMP, in particular the Damascene process described below. The other is defect correction or elimination, as for example sapphire CMP.
A CMP process step is carried out with the help of special polishers, polishing pads and polishing agents which are also referred to in the art as polishing slurries or CMP slurries. A CMP slurry is a composition, which in combination with the polishing pad causes the removal of the material to be polished.
In case that wafers with semiconductor layers are to be polished, the precision requirements for the process step and, thus, the requirements set for the CMP slurry are particularly strict.
A series of parameters are used for evaluating the efficiency of CMP slurries and for characterizing their activity. The material removal rate (MRR), that is the speed with which the material to be polished is removed, the selectivity, that is the ratio of the removal rate of the material to be polished to the removal rates of other materials present, the removal uniformity within a wafer (WIWNU; Within-Wafer-Non-Uniformity) and the removal uniformity from wafer to wafer (WTWNU; Wafer-to-Wafer-Non-Uniformity) as well as the number of defects per unit of area rank among these parameters.
The copper Damascene process is increasingly used for the fabrication of IC (cf., for example, the European patent application EP 1 306 415 A2, page 2, paragraph [0012]). In order to produce the copper circuit paths, it is necessary to remove a copper layer chemically mechanically in this process with the help of a CMP slurry, which process is also called “copper CMP process” in the art. The completed copper circuit paths are embedded in a dielectric. Customarily, a barrier layer customarily consisting of tantalum or tantalum nitride is located between the copper and the dielectric in order to prevent the copper from diffusing into the dielectric layer.
In general, the copper damascene process requires CMP agents providing a good planarization, i.e. a high MMR, combined with a low static etch rate SER. Typically, the desired MRR/SER ratio is approximately 40 or higher. Moreover, the selectivity of the copper CMP agents have to be very high, i.e., the copper MRR must be much higher than the barrier layer MRR. Typically, the selectivity must be greater than 100:1, e.g., about 100:1 to about 400:1.
Even if this property profile is achieved, additional problems arise during copper CMP. These problems are caused by the fact that the conditions and requirements at the end of the CMP process differ from those at the beginning.
Thus, the bulk of the copper is rapidly removed during CMP. During this process, the temperature of the CMP agent increases and, at the end of the process, is about 10 to 20° C. higher than at the beginning. In addition, when hydrogen peroxide is used as the oxidizing agent, its decomposition is accelerated by the increasing copper concentration. On the other hand, the protrusions on the polished surface have almost disappeared. All in all, this renders the CMP slurry much more aggressive than at the beginning.
Quite contrary to this, a much lower MRR is needed at the final stage of the CMP process in order to prevent dishing and/or erosion, in particular during the so-called “over-polishing”, and thus, loss of wafer surface planarity and uniformity. Generally, over-polishing is required to remove residuals of copper from the polished surface. Dishing occurs when the copper and the barrier MRR are disparate and as such, too much copper is removed such that the copper surface in the features is recessed relative to the barrier and/or dielectric surface of the microelectronic device wafer. Oxide erosion occurs when too much dielectric material is removed.
In order to ameliorate or completely avoid these problems, techniques of so-called “soft landing” or “touchdown” have been developed.
Thus, the temperature soft landing technique involves the cooling of the CMP agents and/or the pad. However, this requires additional equipment which increases the overall costs of the manufacturing process.
The chemical soft landing technique involves the use of two CMP agents: an aggressive CMP agent at the beginning of the CMP process and a less aggressive CMP agent at the end of the CMP process. The second, less aggressive CMP agent can be obtained by diluting the first CMP agent (cf. the American patent U.S. Pat. No. 7,161,603 B2) or by adding supplementary additives (cf. the American patent application US2008/0254628 A1). However, this technique requires a particularly careful monitoring of the CMP process in order to detect the appropriate time for applying the second CMP agent.
The mechanical soft landing technique involves the lowering of the downforce and/or the rotational speed of the polishing pad. By way of this technique it was possible to reduce problems like dishing and micro-scratching and to enhance the copper/barrier selectivity. However, due to the increasing demand in lowering the initial downforce, there will be no downforce gap left to achieve the mechanical soft landing. Furthermore, with the high chemical activity of the copper CMP agents, the Prestonian response is getting smaller and smaller. Moreover, it is very costly to upgrade the polishers to handle downforces <3.448 kPa (<0.5 psi).
Consequently, it would be highly desirable to have a CMP agent and a CMP process at hand which could avoid all the disadvantages associated with the prior art soft landing techniques.
The international patent application WO 2006/074248 A2 discloses CMP agents containing composite non-polymeric organic particles as the abrasives. The composite non-polymeric organic particles are engineered to control the events during CMP, in which the particles undergo dynamic changes and provide functions that are not available with conventional inorganic abrasive particles. According to the application, they serve as an abrasive to cut through the surface to-be-polished, as a carrier to deliver a desired ingredient and/or to take away abraded materials from the surface that is being polished. Preferably, the particles provide both a static complexation with the metal surface as well as a dynamic increase in complexing agent concentration. For copper CMP, melamine and its derivatives are preferably used for core structure of the particles. The relevant CMP agents can provide desirable amounts of complexing agents in-situ dynamically. This is accomplished locally according to surface topography. Thus, a region with higher topography that experiences greater local temperature changes or shear force will be provided with a greater amount of complexing agent dynamically, e.g., by the disintegration of the particles at the protrusions of the topography. However, this mechanism leads to an increase in the concentration of the complexing agents during the CMP, which behavior is contrary to the requirements of a soft landing CMP process.
Besides the complexing agents, multiple solid chemical components such as film-forming agents derived from benzotriazole, oxidizing agents, passivating agents or catalytic agents can be encapsulated in the non-polymeric particles. The non-polymeric particles can also have a core-shell structure, wherein the core consisting of, for example, melamine is coated with a solid film-forming agent as the shell. However, no soft landing behavior is disclosed for this embodiment, too.